1. Field of the Invention
The present invention relates to an MPE-FEC (MultiProtocol Encapsulation-Forward Error Correction) RS (Reed-Solomon) decoder and a decoding method thereof and, more particularly, to a technique that reduces the calculation of an error position polynomial of an RS decoder in consideration of hardware complexity and a data processing rate of a reception terminal in case of applying an MPE-FEC scheme to a DVB-S2 standard system.
2. Description of the Related Art
DVB-S2, a broadband satellite communication broadcast convergence service standard, suitable for a Ka band, secures an even larger transmission capacity than a DVB-S, improves service availability through an improvement of a link margin, and supports a bi-directional supplementary broadcast service as well as an HDTV broadcast service. Thus, the demand for a DVB-S2-based digital satellite broadcast service is increasing.
However, in the case of satellite communications, the providing of a service may be interrupted in an NLOS (Non-Line-of-Sight) area such as a tunnel or the downtown area of a city where many skyscrapers are crowded together, so the development of a broadband satellite communications technique suitable for high speed movement and propagation blocking environments is required.
Thus, in order to overcome the high speed movement and propagation blocking environments and provide a reliable and stable service, the DVB-S2-based digital satellite broadcasting system adopts the MPE-FEC scheme defined in DVB-H.
However, the error evaluation polynomial calculation performed for an error correction in an RS decoder of the MPE-FEC increases hardware complexity and degrades calculation speed.